YEESTOR's NVMe controller core (Meissa) is compliant with NVM Express 1.4 specification (NVMe 2.0 Mandatory) and targeted for both enterprise and client SSD markets. It is a highly hardware automated design that requires minimum SW/FW involvement from the CPU. It supports out of order IO read data transfer and can boost the IOPS performance and minimize the latency of SSD controllers. The end-to-end data protection and the error handling mechanism of Meissa enable the robust and reliable SSD controller designs. Meissa is designed with scalability in mind and can easily support throughput up to 32GB/s. Meissa is also highly flexible and can be configured to fit in the requirements of different applications. Meissa is delivered with a complete development package for the ease of use in both FPGA and SoC design.
Key Features
NVMe 1.4 compliant, add on NVMe 2.0 mandatory registers
Support up to 256 functions for SRIOV or physical functions
Support up to 512 namespaces
Support dual ports
Support up to 512 queue pairs
Support up to 4096 outstanding commands
Maximum 64K submission queues entries per submission queue
Maximum 64K completion queues entries per completion queue
Support out-of-order IO read data from flash to host
Support out-of-order IO write command execution
Support Metadata Pointer (MPTR) for +8 and +16
Support IO determination
Weighted round robin with urgent priority class command arbitration
Support PRP and SGL IO command sets
Support E2E data and control path protection
Maximum memory page size of 64KB
Minimum memory page size of 4KB
Support Host Memory Buffer (IP provides extra AXI port for SSD system to access PCIe bus)
Support T10-DIF
Support MSI, MSI-X, and legacy interrupt
Support interrupt coalescing
Support LBA size 512B, 4096B
Support HMB
Support CMB
Pass UNH-IOL compliance test
Functional Block Diagram
Deliverables
RTL code for both ASIC and FPGA
Verilog direct test verification environment
Synthesis script for Synopsys Design Compiler and Xilinx FPGA
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